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[Program doc] SPI-in-Verilog-implementation

Description: SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Platform: | Size: 8192 | Author: 尚林 | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m， 通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m， 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] uart-code-Verilog

Description: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Platform: | Size: 10240 | Author: 李明纬 | Hits:

[VHDL-FPGA-Verilog] uart_EP3C16_FIFO

Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Platform: | Size: 6756352 | Author: 515666524 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart设计 包括调试程序 uart设计 包括调试程序-uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL
Platform: | Size: 2377728 | Author: 石头 | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
Platform: | Size: 1435648 | Author: 冰色火焰 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
Platform: | Size: 36864 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] UART

Description: this a uart verilog HDL design code-this is a uart verilog HDL design code
Platform: | Size: 1136640 | Author: 历程 | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog
Platform: | Size: 1024 | Author: xhly | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Platform: | Size: 35840 | Author: wangli | Hits:

[VHDL-FPGA-Verilog] uart-

Description: 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
Platform: | Size: 30720 | Author: mike | Hits:

[VHDL-FPGA-Verilog] UART

Description: 利用Verilog实现UART收发数据功能-Verilog UART send and receive data functions to achieve
Platform: | Size: 1196032 | Author: 高柯 | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] UART_verilog

Description: 带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequcy, baud_limit applicable to a variety of baud rate, UART
Platform: | Size: 373760 | Author: rick lee | Hits:

[VHDL-FPGA-Verilog] mini-UART

Description: URAT资料，用verilog HDL编写，具有完整的信号描述和功能-URAT data write complete signal description and function, with verilog HDL
Platform: | Size: 51200 | Author: 牛玉祥 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: Verilog HDL设计+Modelsim仿真UART-Verilog HDL Designing+ Modelsim UART simulation
Platform: | Size: 23552 | Author: WangQunfeng | Hits:

[VHDL-FPGA-Verilog] uart

Description: verilog VHDL实现的DE2 uart-Verilog VHDL the uart of the DE2
Platform: | Size: 506880 | Author: jakeli | Hits:

[Software Engineering] FPGA--uart(verilog)

Description: verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
Platform: | Size: 100352 | Author: xiabo | Hits:
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